Attached hereto is a microfiche appendix to the present invention, listing source code for an embodiment of the present invention. The total number of microfiche is 18 pages and the total number of frames is 19 frames.
1. Field of Invention
The present invention relates generally to a method of translating User Defined Primitives (UDPs) in the Verilog format into another format.
2. Description of Related Art
Modern digital design of complex circuits and systems, which can contain millions of interconnected gates, involves a number of techniques for manageable design. Tools using computer-aided design (CAD), hardware description languages (HDL), logic synthesis, and hierarchy design are employed.
A hardware description language (HDL) representation of a circuit is a representation of a circuit in text rather than graphically, enabling a more uniform, portable representation of the circuit, one that can be manipulated by a computer program. Currently, Verilog and VHDL are two IEEE standards of HDLs. The Verilog standard evolves over time, and the present invention is designed to work with the current version, though it is adaptable to work with future versions of the Verilog IEEE standard. HDL may be stylized into xe2x80x9cstructuralxe2x80x9d (e.g. at the gate-level), xe2x80x9cbehavioralxe2x80x9d or xe2x80x9cdataflowxe2x80x9d (typically at the higher level description of a circuit), or any combination of the above. HDL representations are used in logic synthesis, the conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the xe2x80x9cnetlistxe2x80x9d.
An HDL description of a system can be written at an intermediate level referred to as a register transfer language (RTL). A subset of RTL that is used by logic synthesis tools is known as xe2x80x9csnythesizable RTLxe2x80x9d. A logic synthesis tool with a library of components can convert a RTL description into an interconnection of primitive components that implements the circuit, subject to any specified constraints, such as timing, speed, power consumption and area constraints. The output of the logic synthesis tool, after an optimization process referred to as technology mapping, is a so-called netlist of interconnected storage elements, gates, and other functional blocks (note the term xe2x80x9cnetxe2x80x9d is also a keyword in Verilog, and represents a data type comprising a physical connection between structural elements). The netlist output serves as input to physical design tools that physically place the logic elements and route the interconnections between them to produce a manufacturing circuit layout. When programmable parts are employed, such as field-programmable gate arrays, binary information is produced by design tools to program the logic within the parts.
User-defined primitives (UDP) in the Verilog HDL language are user-defined primitive gates that lie outside the xe2x80x9cbuilt-inxe2x80x9d primitive gates provided by Verilog, such as xe2x80x9candxe2x80x9d, xe2x80x9cnandxe2x80x9d, xe2x80x9cnorxe2x80x9d, xe2x80x9corxe2x80x9d, xe2x80x9cxorxe2x80x9d, xe2x80x9cxnorxe2x80x9d, xe2x80x9cbufxe2x80x9d, xe2x80x9cnotxe2x80x9d, xe2x80x9ccmosxe2x80x9d, xe2x80x9cpmosxe2x80x9d, xe2x80x9cnmosxe2x80x9d, xe2x80x9ctranxe2x80x9d and the like. Oftentimes, a designer may wish to translate a Verilog UDP into another format, such as a LogicVision model format.
LogicVision (LV) is a company that produces a suite of test insertion tools that take a netlist, insert structures, and convert the netlist and into a form suitable for testing purposes. The LogicVision suite performs such functions as boundary scan insertion, automatic test pattern generation, logic and memory BIST (Built-In Self Test) insertion. LogicVision uses a particular format, which can be viewed as a subset of the Verilog HDL. The entire Verilog HDL is not understood by LogicVision, and a Verilog model has to be translated into a LogicVision model before it can be used by a LogicVision test insertion tool. The LogicVision model format is easy to describe once the Verilog HDL is translated into basic logic gate descriptions. Thus, concerning the present invention, by translating a circuit described in a Verilog format, having UDPs (User Defined Primitives), into its constituent logic gates, a LogicVision format is easily obtainable, thus making the original circuit description suitable to a test insertion tool such as found in the LogicVision suite.
The present invention relates generally to a method of translating Verilog User Defined Primitives (UDP) to basic logic gates, i.e., gate level primitives, which can be used in another format, such as the LogicVision model format.
Accordingly, an aspect of the present invention is to provide a software program to translate a Verilog UDP (User Defined Primitive) into basic logic gates, in order to allow easier porting into other HDL languages and non-Verilog models, such as the LogicVision model. LogicVision libraries and many other libraries rely primarily on Verilog models, such as the Verilog XL 3.0 library, thus the present invention has value in providing UDP translation for such non-Verilog models.
In a preferred embodiment, the program is in Perl script, and reads in a Verilog source file. On finding a UDP, the script writes out a gate level description of the UDP.
The advantages of the present invention are:
(1) providing a unique method to translate UDPs into gate primitives;
(2) converting into a lowest common denominator between standards, by way of a gate description of a Verilog UDP, enabling porting of a Verilog UDP into another model, such as a LogicVision model;
(3) allowing better handling of xe2x80x98xxe2x80x99 states and event scheduling by using gate level primitives;
(4) providing an interface for other software tools that have difficulty reading in Verilog UDPs.